An integrated circuit (IC) is a set of electronic circuits that integrates a large number of semiconducting transistors into a small chip. Among the most advanced integrated circuits are microprocessors, memory chips, programmable logic sensors, power management circuits, etc. Advances in IC technology have led to size reduction of transistors, enabling greater densities of devices and circuits in IC chips and enhanced performance.
Metal wires have been used for IC interconnects since the invention of IC in early 70's. For the first several decades, the wires were manufactured with aluminum, but since the late 90's copper wires have been replacing aluminum for most of the ICs. Initially, due to the larger design rules, the wires were several microns wide. Currently, at 14 nm FinFET ICs, the copper interconnect wires on lower interconnect layers are about 30 nm wide. At the upcoming 7 nm and 5 nm technology nodes, the wire width is expected to reduce down to 15 nm, where ˜4 nm are taken by barrier layers that sheath the copper, with just 11 nm left for the copper wire. At such wire widths, copper resistivity is expected to more than double with respect to bulk copper resistivity. Resistivity is sharply increasing with the wire width scaling due to the increased electron scattering at the copper interfaces and grain boundaries, and grain size is proportional to the wire width.
The increase in wire resistance leads to increased delay of signal propagation through the wire from one circuit block to the next. To mitigate it, circuit designers are using so-called via pillars which is a structure that contains several vias propagating a connection from transistors that are below metal 0 to the high metal layers, say metal 5 or metal 6. The wires at high metal layers are wider and therefore provide lower resistance and lower signal delay. However, wider wires mean that there are fewer such wires available to connect circuit elements to each other. Besides, the via pillars take a considerable area and therefore increase the cost of IC manufacturing. An accurate model to quantify different interconnect routing options is necessary to optimize the performance of each particular IC to achieve its spec requirements.
A simulation model has been developed for modeling resistance of an interconnect wire using a 3-D coordinate system as described in U.S. Non-Provisional application Ser. No. 15/823,252 filed on Nov. 27, 2017, the entire contents of which are hereby incorporated by reference herein. Roughly described, for each of a plurality of volume elements in the specified structure, the simulation model specifies a location and one a first and second materials of the interconnect having specified resistivities, and for each volume element generates a model resistivity for the volume element as a function of resistivity of volume elements within a neighborhood of the volume element and a specified transition region length λ. The model prefers accuracy over computational inefficiency as it assumes local metal resistivity inside the wire to be an exponential function of the distance from wire surface, with a characteristic length of about 3 nanometers. To be accurate with such a sharply varying function, very fine mesh spacing may be needed, which results in a large overall number of mesh points and a long computing time.
It is therefore desirable to provide an efficient simulation tool that can calculate the resistance of IC interconnects on a coarse mesh.